--
-- VHDL Architecture Fietscomputer_lib.f33to1.v
--
-- Created:
--          by - John.UNKNOWN (EPOX)
--          at - 20:03:16 04/29/2009
--
-- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY s_f33to1 IS
  
  PORT( 
  clk       : IN     STD_LOGIC;
  rst       : IN     STD_LOGIC;
  
  clk1MHz   : OUT    STD_LOGIC
  );
  
END ENTITY s_f33to1;

--
ARCHITECTURE v OF s_f33to1 IS

SIGNAL  q    :  NATURAL RANGE 0 TO 32;

BEGIN
  
  
  
  PROCESS(rst, clk)
    BEGIN
      IF rst = '1' THEN
        q <=  0;
      ELSIF RISING_EDGE(clk) THEN
        
        IF q = 32 THEN
          q <= 0;
        ELSE
          q <= q + 1;
        END IF;    
        
      END IF;
    END PROCESS;
    
    
    
    
    PROCESS(rst, clk)
      BEGIN
        IF rst = '1' THEN
          clk1MHz <=  '0';
        ELSIF RISING_EDGE(clk) THEN
          
          IF q = 16 THEN
            clk1MHz <= '1';
          ELSIF q = 32 THEN
            clk1MHz <= '0';
          END IF;    
          
        END IF;
      END PROCESS;
      
      
      
      
      
    END ARCHITECTURE v;
    
    
    
    